H. T. Vergos - Professor

Logic Design II

In Logic Design II, we turn our attention into sequential logic. HDLs are used as a description vehicle for the designs.

Latches and flip flops are firstly introduced and analyzed. The operation and design of synchronous sequential machines is then presented, followed by the structures of HDLs that support it. The course then discusses commonly used sequential designs ((shift) registers, counters, ...), memory construction by 2-D and 3-D designs. A brief look at sequential programmable logic devices, field programmable gate arrays and asynchronous sequential circuits completes the course.

Marks are based on both a written test and on homeworks assigned to small groups of students.

• The written test focuses on the ability to build a FSM that implements some basic function, such as string recognition or input counting and on comprehending the functionality of basic sequential elements.
• The homeworks are of substantial difficulty in order not to have a single obvious solution, that enables our students to consider different state encodings, use of different FFs and coding styles.