H. T. Vergos - Professor

Conferences / Symposia Publications

• H. T. Vergos and D. Nikolos, Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache, IEEE International Computer Performance and Dependability Symposium (IPDS '95), Erlangen, Germany, April 24-26, 1995, pp. 326-332.

• D. Nikolos, H. T. Vergos, A. Vazaios and S. Voulgaris, Yield - Performance tradeoffs for VLSI processors with partially good two level caches, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '96), Boston, MA, USA, November 6-8, 1996, pp. 53-57.

• H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, On Path Delay Fault Testing of Multiplexer - Based Shifters, 9^th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March 4-6, 1999, pp. 20-23.

• D. Nikolos, Th. Haniotakis, H. T. Vergos and Y. Tsiatouhas, Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks, Design, Automation and Test in Europe Conference and Exhibition (DATE '99), Munich, Germany, March 9-12, 1999, pp. 112-116.

• H. T. Vergos, M Bellos and D. Nikolos, Path Delay Fault Testing of Benes Multistage Interconnection Networks, 6^th IEEE International Conference on Electronics, Circuits and Systems (ICECS '99), Pafos Cyprus, September 5-8, 1999, Volume II, pp. 1097 - 1100.

• Th. Haniotakis, H. T. Vergos, Y. Tsiatouhas, D. Nikolos and M. Nicolaidis, Easily Testable Carry-Save Multipliers with respect to Path Delay Faults, 2^nd Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8 1999, pp. 13-16.

• G. Sidiropoulos, H. T. Vergos and D. Nikolos, Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers, 8^th Asian Test Symposium (ATS '99), Shanghai, China, November 16 -18 1999, pp. 47-52.

• E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas and Th. Haniotakis, Path Delay Fault Testable Modified Booth Multipliers, XIV Design of Circuits and Integrated Systems Conference (DCIS '99), Palma de Mallorca, Spain, November 16-19 1999, pp. 301-306.

• D. Bakalis, H. T. Vergos, D. Nikolos, X. Kavousianos and G. Ph. Alexiou, Low power dissipation in BIST schemes for modified Booth multipliers, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'99), Albuquerque, New Mexico, USA, November 1-3, 1999, pp. 121-129.

• T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas and H. T. Vergos, A Class of Easily Testable Path Delay Fault Testable Circuits, 2000 Southwest Symposium on Mixed - Signal Design (ISSMSD 2000), San Diego, California, USA, February 27-29 2000, pp. 165-170.

• D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Ph. Alexiou, Low Power BIST for Wallace-Tree based Fast Multipliers, 1^st IEEE International Symposium on Quality Electronic Design (ISQED 2000), San Jose, California, USA, March 20-22, 2000, pp. 433-438.

• H. T. Vergos, Early Design Phase of a Surveillance System built around Digital Wireless Subnetworks, Design Automation and Test in Europe (DATE 2000), Paris, France, March 27-30, 2000, pp. 133-137.

• D. Bakalis, M. Bellos, H. T. Vergos, D. Nikolos and G. Alexiou, A Macro Generator for Arithmetic Cores, XV Design of Circuits and Integrated Systems Conference (DCIS '2000), Montpelier, France, November 21-24, 2000, pp. 734-739.

• C. Efstathiou and H. T. Vergos, Modified Booth 1's Complement and Modulo 2ⁿ-1 Multipliers, 7^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS '2K), Beirut, Lebanon, December 17-20, 2000, Volume II, pp. 637-640.

• D. Bakalis, D. Nikolos, H. T. Vergos and X. Kavousianos, On Accumulator-based Bit-Serial Test Response Compaction Schemes, IEEE International Symposium on Quality Electronic Design (ISQED 2001), San Jose, California, USA, March 26-28, 2001, pp. 350-355.

• H. T. Vergos, C. Efstathiou and D. Nikolos, High Speed Parallel-Prefix Modulo 2ⁿ+1 Adders for Diminished-One Operands, 15^th IEEE Symposium on Computer Arithmetic (ARITH-15), Vail, Colorado, June 11-13, 2001, pp. 211-217.

• H. T. Vergos, A 200-MHz RNS Core, European Conference on Circuit Theory and Design (ECCTD '01), "Circuit Paradigm in the 21^st Century", August 28 - 31, 2001, Espoo, Finland, Vol. II, pp. 249 - 252.

• C. Efstathiou, H. T. Vergos and D. Nikolos, On the Design of Modulo 2ⁿ±1 Adders, 8^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2001), Malta, September 2-5, 2001, Vol. I, pp. 517-520.

• C. Efstathiou, H. T. Vergos and D. Nikolos, Ling Adders in CMOS standard cell technologies, 9^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2002), Dubrovnik, Croatia, September 15-18, 2002, Vol. II, pp. 485-489.

• H. T. Vergos, C. Efstathiou and D. Nikolos, Fast Parallel-Prefix Modulo 2ⁿ+1 adders, XVII Conference on Design of Circuits and Integrated Systems (DCIS' 2002), Santander, Spain, November 19-22, 2002, pp. 65-70.

• G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo 2ⁿ-1 Adders, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, Vol. V, pp. 225-228.

• D. G. Nikolos, D. Nikolos, H. T. Vergos and C. Efstathiou, Efficient BIST Schemes for RNS Datapaths, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, Vol. V, pp. 573-576.

• G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, A Family of Parallel-Prefix Modulo 2ⁿ-1 Adders, 2003 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 24-26, 2003, pp. 326-336.

• D. G. Nikolos, D. Nikolos, H. T. Vergos and C. Efstathiou, An Efficient BIST scheme for High-Speed Adders, 9^th IEEE International On-Line Testing Symposium (IOLTS 2003), Kos, Greece, July 7-9, 2003, pp. 89-93.

• H. T. Vergos, On the Efficiency of Parallel-Prefix Adders, 16^th European Conference on Circuits Theory and Design, (ECCTD'03), Krakow, Poland, 1-4 September 2003, Vol. II, pp. 265-268.

• C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos and D. Nikolos, Efficient Modulo 2ⁿ+1 Tree Multipliers for Diminished-1 Operands, 10^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS'03), Sharjah, United Arab Emirates, December 14-17, 2003, Vol. III, pp. 200-203.

• H. T. Vergos and C. Efstathiou, Diminished-1 Modulo 2ⁿ+1 Squarer Design, Euromicro Symposium on Digital System Design (DSD '04), Rennes, France, August 31-September 3, 2004, pp. 380-386.

• D. Adamidis and H. T. Vergos, Modulo 2ⁿ-1 Multiplication / Sum-of-Squares Units, European Conference on Circuit Theory and Design 2005 (ECCTD 2005), August 29-September 2, 2005, Vol. II, pp. 143-146.

• G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos and C. Efstathiou, New Architectures for Modulo 2ⁿ-1 Adders, 12^th IEEE International Conference on Electronics, Circuits and Systems, Grammath, Tunisia, December 11-14, 2005.

• H. T. Vergos and C. Efstathiou, Novel Modulo 2ⁿ+1 Multipliers, 9^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30-September 1, 2006, pp. 168-175.

• H. T. Vergos and C. Efstathiou, Efficient Modulo 2^k+1 Squarers, XXI Conference on Design of Circuits and Integrated Systems (DCIS 2006), Barcelona, November 22-24, 2006.

• H. T. Vergos, An Efficient BIST Scheme for Non-Restoring Array Dividers, 10^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2007), August 29-31, 2007, Lubeck, Germany, pp. 664-667.

• H. T. Vergos, Fast Modulo 2ⁿ+1 Adder Architectures, XXII Conference on Design of Circuits and Integrated Systems, Sevilla, Spain, November 21-23, 2007, pp. 476–481.

• H. T. Vergos, D. Bakalis and C. Efstathiou, Efficient Modulo 2ⁿ+1 Multi-operand Adders, 15^th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, August 31 – September 3, 2008, pp. 694–697.

• H. T. Vergos and D. Bakalis, On the Use of Diminished-1 Adders for Weighted Modulo 2ⁿ+1 Arithmetic Components, 11^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2008), Parma, Italy, September 3–5, 2008, pp. 752–759.

• A. Spyrou, D. Bakalis and H. T. Vergos, Efficient Architectures for Modulo 2ⁿ-1 Squarers, 16^th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.

• E. Vassalos, D. Bakalis and H. T. Vergos, Novel Modulo 2ⁿ+1 Subtractors, 16^th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.

• E. Vassalos, D. Bakalis and H. T. Vergos, SUT-RNS Forward and Reverse Converters, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), Kefallonia, Greece, July 5–7, 2010, pp. 11–16.

• H. T. Vergos, A Family of Area-Time Efficient Modulo 2ⁿ+1 Adders, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), Kefallonia, Greece, July 5–7, 2010, pp. 442–443.

• D. Bakalis and H. T. Vergos, Area Efficient Multi-Moduli Squarers for RNS, 13^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2010), Lille, France, September 1–3, 2010, pp. 408-411.

• D. Bakalis and H. T. Vergos, Diminished-1 Modulo 2ⁿ+1 Multiply-Add Circuits, XXV Conference on Design of Circuits and Integrated Systems (DCIS 2010), Lanzarotte, Spain, November 17-19, 2010, pp. 289-294.

• H. T. Vergos and D. Bakalis, Area–Time Efficient Multi-Moduli Adder Design, XXV Conference on Design of Circuits and Integrated Systems (DCIS 2010), Lanzarotte, Spain, November 17-19, 2010, 295-300.

• E. Vassalos, D. Bakalis and H. T. Vergos, On the Use of Double LSB and Signed-LSB Encodings for RNS, 17^th International Conference on Digital Signal Processing (DSP 2011), Corfu, Greece, July 6-8, 2011, pp. 1-6.

• E. Vassalos, D. Bakalis and H. T. Vergos, Modulo 2ⁿ+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion, 14^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2011), Oulu, Finland, August 31-September 2, 2011, pp. 468-475.

• E. Vassalos, D. Bakalis and H. T. Vergos, Configurable Booth–Encoded Modulo 2ⁿ ± 1 Multipliers, 8^th Conference on Ph.D. Research in Microelectronics & Electronics (PRIME 2012), Aachen, Germany, June 12–15 2012, pp. 107–110.

• H. T. Vergos, O. Giannou and D. Bakalis, Squarers in QCA Nanotechnology, 12^th IEEE International Conference on Nanotechnology (IEEE-NANO), Birmingham, UK, August 20–23, 2012, pp. 689–694.

• E. Vassalos, D. Bakalis and H. T. Vergos, SUT-RNS Residue-to-Binary Converters Design, 15^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2012), Cesme, Turkey, September 5-8, 2012, pp. 65–72.

• E. Vassalos, D. Bakalis and H. T. Vergos, Reverse Converters for RNSs with Diminished-One Encoded Channels, IEEE Region 8 Eurocon 2013 Conference, Zagreb, Croatia, July 1–4, 2013, pp. 1798–1805.

• E. Vassalos, D. Bakalis and H. T. Vergos, RNS Assisted Image Filtering and Edge Detection, 18^th IEEE International Conference on Digital Signal Processing (DSP 2013),, Santorini, Greece, July 1–3, 2013, pp. 1–6.

• A. Thanos and H. T. Vergos, Fast Parallel-Prefix Ling-Carry Adders in QCA Nanotechnology, 20^th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2013), Abu Dhabi, UAE, December 8-11, 2013, pp. 565–568.

• A. Bikos and H. T. Vergos, Easily Verified IP Watermarking, Design & Technology of Integrated Systems at Nanoscale Era (DTIS 2014), Santorini, Greece, May 6-8, 2014.

• G. Blanas and H. T. Vergos, Extending the Viability of Power Signature-Based IP Watermarking in the SoC Era, 23^rd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), Monte Carlo, Monaco, December 10-14, 2016, pp. 281–284.

• K. Velonis and H. T. Vergos, A Comparison of Softmax Proposals, 2^nd IEEE International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME) Maldives, November 16-18, 2022, pp. 1–6.